1. Field
The following description relates to an apparatus for output buffering having a half-swing rail-to-rail structure, and more specifically to an apparatus for output buffering having a half-swing rail-to-rail structure that features a high slew rate and low power consumption.
2. Description of Related Art
Generally, for an integrated circuit (IC) to drive a panel of display device, a slew rate is arising as an important factor in its operation, due to an increase of load capacitance and a reduction of horizontal period, according to the increase. In electronics, a slew rate is defined as the maximum rate of change of output voltage per unit of time. Such an integrated circuit may be referred to as a Display Driver IC (DDI) or display driver device.
Also, from the viewpoint of a mounting environment of a panel DDI, conventionally, a Source IC was configured to drive one liquid crystal. More recently, a Source IC may drive three liquid crystals, which requires that an IC drives two more liquid crystals. Due to these increased demands that are placed on the DDI, realization of a fast slewing time becomes necessary.
Also, a display driver device may be designed to feature a reduction of current consumption, a high slew rate, a fast slewing time, or a fast settling time, since realization of fast slewing time and low power consumed therein are also design goals of a display driver device.
FIG. 1 illustrates a plan view indicating a Liquid Crystal Display device.
A Liquid Crystal Display device (LCD) offers advantages such as miniaturization, thinness and low power consumption. Hence, LCD technology is used, for example, for an LCD screen panel of a notebook computer and an LCD TV. Specifically, an LCD device, whose type is active matrix uses a Thin Film Transistor (TFT) as a switch element and is a display technology that is suitable for displaying a moving image.
When referring to FIG. 1, a Liquid Crystal Display device (LCD) 1 comprises a liquid crystal panel 2, source drivers (SD) having many source lines (SL) respectively, and gate drivers (GD) having many gate lines (GL) respectively. A source line (SL) may be referred to a data line or a channel.
Each of the source drivers (SD) drives source lines (SL) arranged on the liquid crystal Panel 2. Each of the gate drivers (GD) drives gate lines (GL) arranged on a liquid crystal panel 2.
The Liquid crystal Panel 2 comprises many pixels 3. Each of the pixels 3 comprises a switch transistor (TR), a storage capacitor (CST) for reducing a current leakage from the liquid crystal, and a liquid crystal capacitor (CLC). A switch transistor (TR) is turned on and turned off in response to a signal driving a gate line (GL). A terminal of the switch transistor (TR) that is turned on and turned off by the signal from the gate line (GL) is connected to a source line (SL).
A storage capacitor (CST) is connected between another terminal of the switch transistor (TR) and a grounding voltage (VSS), and the liquid crystal capacitor (CLC) is connected between another terminal of the switch transistor (TR) and a common voltage (VCOM). In an example, the common voltage (VCOM) is a power voltage, such as VDD/2.
The load of each of the source lines (SL) connected to the pixels 3 arranged on the liquid crystal panel 2 may be modeling by representing it using parasitic resistors and parasitic capacitors.
FIG. 2 illustrates a schematic view indicating an apparatus for output buffering.
When referring to FIG. 2, a source driver 50 includes an output buffer 10, an output switch 11, an output protection resistor 12 and a load 13 connected to a source line. The output buffer 10 delivers an analog moving image signal to a corresponding output switch 11 for amplification. The output switch 11 outputs the amplified analog moving image signal as a signal driving a source line, in response to an activation of a signal controlling an output switch, such as switch (OSW) and/or switch (OSWB). The signal driving source line is provided with the load 13 connected to the source line. As illustrated in FIG. 2, the load 13 is modeled as parasitic resistors (RL1 to RL5) and parasitic capacitors (CL1 to CL5) such that the parasitic resistors (RL1 to RL5) and parasitic capacitors (CL1 to CL5) are connected in a ladder type structure.
However, according to this example approach, the output switch 11 has a plurality of transmission switches. Therefore, a slew rate becomes low, due to a resistance element resulting from the use of the plurality of transmission switches. Thus, the slewing time increases, which potentially interferes with the functionality of the device. Also, another issue that occurs is that elevating the slew rate potentially increases current consumption, which may also be detrimental to the functionality of the device.